Senior Principal Hardware Systems Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

The explosive growth of AI workloads is fundamentally reshaping how server platforms are designed — demanding unprecedented bandwidth, accelerator density, and intelligent connectivity at every layer of the stack. Astera Labs is powering this transformation with purpose-built connectivity solutions that enable the world's most advanced AI and cloud infrastructure, and we need exceptional hardware systems engineers to help architect what comes next.

The AI Platform Solutions Group is seeking a Senior Principal Hardware Systems Engineer to lead the architecture and delivery of high-performance compute platforms with deep focus on PCIe subsystem design, GPU/accelerator integration, high-speed Ethernet networking, and system-level platform development. You will own the end-to-end system design from architecture definition through bring-up and validation, working at the critical intersection of compute, networking, storage, and Astera Labs' connectivity portfolio — including our PCIe retimers, switches, and fabric controllers.

This role combines hands-on engineering depth with system-level architectural thinking. You will drive complex platform development across hardware, firmware, and system management domains while collaborating with silicon vendors, hyperscalers, and cross-functional engineering teams. If you want to architect the AI platforms that are defining the future of data center compute, this is your opportunity.

Key Responsibilities

System Architecture & PCIe Platform Design

Lead system architecture and design for high-performance compute platforms optimized for AI and accelerator-driven workloads

Design and integrate PCIe-based subsystems including GPU, accelerator, and high-speed I/O components leveraging PCIe Gen5/6 technologies

Define and implement GPU-enabled server platforms for AI training, inference, and HPC workloads

Architect and optimize high-speed Ethernet networking interfaces (25G/100G/400G+) within platform designs

Hardware Development & Validation

Drive system-level integration across compute, networking, and storage subsystems

Develop and validate FPGA-based solutions for system control, monitoring, and acceleration

Lead system bring-up, debug, and validation in lab environments

Troubleshoot complex hardware and performance issues across high-speed signaling, power, thermal, and interconnect domains

Platform Management & Cross-Functional Leadership

Define and implement platform management solutions including BMC integration, telemetry, health monitoring, and system-level diagnostics

Collaborate with cross-functional teams spanning hardware, firmware, BIOS, and OS to ensure seamless platform integration

Partner with silicon vendors, OEMs, and hyperscalers on custom platform development aligned with Astera Labs' connectivity ecosystem

Drive performance optimization across PCIe topology, accelerator interconnects, and memory subsystems

Basic Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field

12+ years of experience in hardware engineering, system design, or platform architecture

Strong expertise in PCIe architecture and subsystem design

Hands-on experience with GPU integration and accelerator-based system development

Experience with high-speed Ethernet networking architecture (10G/25G/100G or higher)

Hands-on experience with FPGA design including architecture, simulation, and validation

Proven experience with system bring-up, hardware debugging, and platform validation

Solid understanding of high-speed signaling, interconnects, power, and thermal optimization

Experience with system management frameworks (BMC, telemetry, monitoring)

Preferred Qualifications

Master's degree in Electrical Engineering, Computer Engineering, or a related field

Experience in AI/ML infrastructure, GPU clusters, or hyperscale data center server platforms

Knowledge of PCIe Gen5/Gen6, RDMA, RoCE, or similar high-performance networking technologies

Experience with custom platform development or customer-specific hardware designs

Familiarity with Astera Labs' connectivity solutions (retimers, switches, fabric controllers) or similar high-speed interconnect products

Experience working with global hardware development teams

Exposure to platform lifecycle management and fleet-level system diagnostics

 
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.